Output buffer circuit and method for avoiding voltage overshoot

ABSTRACT

An output buffer circuit for avoiding voltage overshoot includes an input stage, an output bias circuit, an output stage, a clamp circuit, and a control unit. The input stage includes a positive input terminal, for receiving an input voltage, and a negative input terminal. The input stage generates a current signal according to the input voltage. The output bias circuit is coupled to the input stage, for generating a dynamic bias according to the current signal. The output stage is coupled to the input stage and the output bias circuit, including an output terminal, reversely coupled to the positive input terminal, and at least one output transistor, coupled to the output bias circuit and the output terminal, for providing a driving current to the output terminal according to the dynamic bias to generate an output voltage.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an output buffer circuit for avoidingvoltage overshoot, and more particularly, to an output buffer circuitthat prevents leakage currents from changing a systematic offset voltageby timely closing a clamping circuit.

2. Description of the Prior Art

An output stage of a present display driver adopts an operationalamplifier circuit to rapidly charge and discharge a load end, such thatdriving capability of the display driver is enhanced. However, if innercurrents of the operational amplifier cannot be recovered immediately,the rapid charging or discharging of the load end would a voltageovershoot. In general, a clamping circuit is added between an outputterminal of the operational amplifier and an input terminal of theoutput stage thereof to avoid the voltage overshoot. However, under asituation that the operational amplifier has full swing output, theclamping circuit may not be completely closed, resulting in certainleakage currents (in approximate nA degree). For low power application,such leakage currents may change a systematic offset voltage of thedisplay driver.

Please refer to FIG. 1. FIG. 1 is a schematic diagram of an operationalamplifier 10 according to the prior art. The operational amplifier 10 isa two stage amplifier, and includes an input stage 11, an output biascircuit 12, an output stage 13 and a clamping circuit 14. The inputstage 11 is a differential input stage having a rail-to-rail inputrange, and includes a positive input terminal AVP and a negative inputterminal AVN. The input stage 11 includes input transistors N1, N2, P1and P2 coupled to the input terminals AVP and AVN and bias transistorsN3 and P3 coupled to the bias terminals VBN1 and VBP1, respectively. Theinput stage 11 generates a current signal IAB according to an inputvoltage received by the positive input terminal AVP. The output biascircuit 12 is coupled to the input stage 11, for generating a dynamicbias VAB between nodes AA and AB (i.e. a voltage difference between thenode AA and the node AB) according to the current signal IAB. The outputstage 13 is a class AB output stage composed of transistors P9 and N9,and includes an input output terminal AVF reversely coupled to thenegative input terminal AVN of the input stage 11. The output stage 13provides a driving current to the output terminal AVF according to thedynamic bias VAB, so as to generate an output voltage. The clampingcircuit 14 consists of transistors POS1, POS2, NOS1, and NOS2, formaintaining the output voltage of the operational amplifier 10 within apredefined range, so as to avoid the voltage overshoot.

When the operational amplifier 10 charges the load, such as receiving ahigh level input voltage, a voltage of the positive input terminal AVPincreases, such that the current signal IAB flowing through the outputbias circuit 12 decreases, and results in decrease of voltages of thenodes AA and AB. Under such circumstances, the output stage 13 increasesthe driving current for the output terminal AVF to enhance the outputvoltage of the operational amplifier, as shown by solid lines in FIG. 1.On the contrary, when the operational amplifier 10 discharges the load,such as receiving a low level input voltage, the voltage of the positiveinput terminal AVP decreases, such that the current signal IAB flowingthrough the output bias circuit 12 increases, and results in increase ofthe voltages of the nodes AA and AB. Under such circumstances, theoutput stage 13 reduces the driving current for the output terminal AVFto decrease the output voltage of the operational amplifier, as shown bydot lines in FIG. 1.

Under normal conditions, a level of the output voltage makes overdrivevoltages of the transistors POS2 or NOS2 smaller than threshold voltagesthereof, i.e. (AVF-VBPOS)<Vthp or (VBNOS-AVF)<Vthn, and results in thetransistors POS2 or NOS2 being closed. Hence, the clamping circuit 14has no effects on the charging and discharging operations of theoperational amplifier. Whereas, when the level of the output voltageexceeds a predefined range, the overdrive voltages of the transistorsPOS2 or NOS2 are larger than the threshold voltages thereof, i.e.(AVF-VBPOS)>Vthp or (VBNOS-AVF)>Vthn, which results in the transistorsPOS2 or NOS2 being on. In this case, currents flowing from the outputterminal AVF into the nodes AA or AB help the voltages of the nodes AAor AB to return to a normal level, so as to alleviate the voltageovershoot.

However, incases that the operational amplifier has full swing output,the transistors POS2 or NOS2 may not be completely closed, resulting ina certain leakage currents. Take the discharging operation as anexample, the output voltage of the operational amplifier may be as lowas 0.1 volt, thereby the transistors NOS1 and NOS2 cannot be completelyclosed, and results in a certain currents flowing through thetransistors NOS1 and NOS2 (from the output terminal AVF into the nodeAB). For the low power application, currents of each path in theoperational amplifier become lower and lower, thereby it becomes obviousthat variations of currents flowing through the transistors P11 and N11and a variation of the overdrive voltage caused by the leakage currents,so as to influence a bias status and a static current of the outputstage 13. With a change to the static current of the output stage 13, atransconductance of the output stage 13 and a gain of the operationalamplifier would also vary. The gain of the operational amplifierdirectly influences a systematic offset voltage of the operationalamplifier.

In brief, for the low power application, the current of each path of theoperational amplifier becomes lower with time. In the full swing outputcase, the clamping circuit cannot be completely closed, resulting in amore obvious change to the static current of the output bias circuit.Accordingly, the gain of the whole operational amplifier changes, so asto influence the systematic offset voltage of the operational amplifier.

SUMMARY OF THE INVENTION

It is therefore a primary objective of the claimed invention to providean output buffer circuit and method for avoiding voltage overshoot.

The present invention discloses an output buffer circuit for avoidingvoltage overshoot. The output buffer circuit includes an input stage, anoutput bias circuit, an output stage, a clamp circuit, and a controlunit. The input stage includes a positive input terminal, for receivingan input voltage, and a negative input terminal. The input stagegenerates a current signal according to the input voltage. The outputbias circuit is coupled to the input stage, for generating a dynamicbias according to the current signal. The output stage is coupled to theinput stage and the output bias circuit, including an output terminal,reversely coupled to the positive input terminal, and at least oneoutput transistor, coupled to the output bias circuit and the outputterminal, for providing a driving current to the output terminalaccording to the dynamic bias to generate an output voltage. The clampcircuit is coupled to the input stage, the output bias circuit and theoutput stage, for drawing currents from the output terminal to help thecurrent signal to return the dynamic bias to a proper level when theoutput voltage exceeds a predefined range. The control unit is coupledto the clamp circuit, for activating the clamp circuit when the outputbuffer circuit receives the input voltage and for deactivating the clampcircuit when the output voltage reaches a steady state.

The present invention further discloses a method of avoiding voltageovershoot for an output buffer circuit. The output buffer circuitincludes an input stage, an output stage and a clamp circuit. The inputstage generates a current signal according to an input voltage. Theoutput stage generates an output voltage according to the currentsignal. The clamp circuit is coupled to the input stage and the outputstage, for clamping the output voltage within a predefined range. Themethod includes activating the clamp circuit when the input voltage isreceived, starting to output the output voltage, and deactivating theclamp circuit when the output voltage reaches a steady state.

These and other objectives of the present invention will no doubt becomeobvious to those of ordinary skill in the art after reading thefollowing detailed description of the preferred embodiment that isillustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of an operational amplifier according tothe prior art.

FIG. 2 is a schematic diagram of an output buffer circuit capable ofimproving voltage overshoot according to an embodiment of the presentinvention.

FIG. 3 is a timing diagram of signals of the output buffer circuit inFIG. 2.

FIG. 4 is a schematic diagram of the control unit in FIG. 1 according toan embodiment of the present invention.

FIG. 5 is a schematic diagram of the control unit in FIG. 1 according toanother embodiment of the present invention.

FIG. 6 is a schematic diagram of a voltage overshoot elimination processaccording to an embodiment of the present invention.

DETAILED DESCRIPTION

Please refer to FIG. 2. FIG. 2 is a schematic diagram of an outputbuffer circuit 20 capable of improving voltage overshoot according to anembodiment of the present invention. The output buffer circuit 20includes an input stage 21, an output bias circuit 22, an output stage23, a clamping circuit 24 and a control unit 25. The input stage 21 is adifferential input stage having a rail-to-rail input range, and includesa positive input terminal AVP and a negative input terminal AVN. Thestructure of the input stage 21 is similar to the structure of the inputstage 11, so the elements and signals having similar functions aredenoted by the same symbols. The input stage 11 21 generates a currentsignal IAB according to an input voltage received by the positive inputterminal AVP. The output bias circuit 22 is coupled to the input stage21, for generating a dynamic bias VAB between nodes AA and AB (i.e. avoltage difference between the node AA and the node AB) according to thecurrent signal IAB. The output stage 23 is a class AB output stagecomposed of transistors P9 and N9, and includes an input terminal AVFreversely coupled to the negative input terminal AVN of the input stage21. The output stage 23 provides a driving current to the outputterminal AVF according to the dynamic bias VAB, so as to generate anoutput voltage. The clamping circuit 24 consists of transistors POS1,POS2, NOS1, and NOS2, for drawing currents from the output terminal AVFto help the current signal IAB for returning the dynamic bias to apredefined level when the output voltage exceeds a predefined range, soas to avoid the voltage overshoot. The control unit 25 is coupled to theclamp circuit 24, for activating the clamp circuit 24 when the outputbuffer circuit 20 receives the input voltage and for deactivating theclamp circuit 24 when the output voltage reaches a steady state. Pleasenote that the input stage 21, the output bias circuit 22, the outputstage 23 and the clamping circuit 24 are merely an exemplary embodimentof the present invention, which can be implemented by any kind ofoperational amplifier circuit, and is not limited to this.

In the embodiment of the present invention, the transistors POS1 andPOS2 are P-type metal-oxide-semiconductor field-effect (MOSFET)transistors, for clamping the output voltage under a predefined highvoltage level; while the transistors NOS1 and NOS2 are N-type MOSFETs,for clamping the output voltage over a predefined low voltage level. Agate of the transistor POS2 is coupled to an operating bias VBPOS, whilea gate of the transistor NOS2 is coupled to an operating bias VBNOS. Theoperating biases VBPOS and VBNOS are switched by the control unit 25.When the output buffer circuit 20 receives the input voltage, thecontrol unit 25 switches the operating biases VBPOS and VBNOS to anormal bias level to activate the clamping circuit 24; whereas, when avoltage level of the output terminal AVF reaches a steady state, thecontrol unit 25 switches the operating biases VBPOS and VBNOS to a powersupply voltage VDDA and a ground voltage GNDA, respectively. Such thatthe transistors POS2 and NOS2 are closed, so as to deactivate theclamping circuit 24.

Please refer to FIG. 3. FIG. 3 is a timing diagram of signals of theoutput buffer circuit 20 in FIG. 2. First, in a data loading phase, theoutput buffer circuit 20 receives an analog voltage outputted from apre-stage circuit. Meanwhile, the operating biases VBPOS and VBNOS areswitched to the normal bias level, respectively. Such that the clampingcircuit 24 is activated to prevent the voltage level of the outputterminal AVF from the voltage overshoot. Next, when the voltage level ofthe output terminal AVF reaches the steady state, the control unit 25switches the operating biases VBPOS and VBNOS to the power supplyvoltage VDDA and the ground voltage GNDA, respectively. Such that thetransistors POS2 and NOS2 are closed compulsorily, so as to eliminatecurrents flowing through the transistors POS1, POS2, NOS1, and NOS2. Asa result, when the output voltage reaches the steady state, theembodiment of the present invention can prevent the leakage currents ofthe clamping circuit 24 from attacking the bias status of the outputstage and the gain of the whole operational amplifier.

In the embodiment of the present invention, the control unit 25 candetermine whether the output voltage reaches the steady state byfollowing two methods, and is not limited to these. One method isdetermining the output voltage reaches the steady state when the outputbuffer circuit 20 receives the output input voltage for a predefinedtime; while the other method is determining whether the output voltagereaches the steady state by detecting voltage difference between theoutput terminal AVF and the positive input terminal AVP after the outputbuffer circuit 20 receives the input voltage.

For example, please refer to FIG. 4. FIG. 4 is a schematic diagram ofthe control unit 25 in FIG. 1 according to an embodiment of the presentinvention. For clarity, the input stage 21, the output bias circuit 22,the output stage 23 and the clamping circuit 24 in FIG. 1 arerepresented by an operational amplifier 41. As shown in FIG. 4, thecontrol unit 25 includes a trigger circuit 252 and a timer 254. Thetrigger circuit 252 is used for generating a trigger signal T1 when theoutput buffer circuit 20 receives the input voltage, such as enteringthe data load phase. The timer 254 is coupled to the trigger circuit252, for calculating the predefined time according to the trigger signalT1, so as to provide a basis for the control unit 25 to determinewhether the output voltage reaches the steady state. As a result, afterthe predetermined time, the control unit 25 is able to switch theoperating biases VBPOS and VBNOS to the power supply voltage VDDA andthe ground voltage GNDA, respectively, so as to deactivate the clampingcircuit 24.

Please refer to FIG. 5. FIG. 5 is a schematic diagram of the controlunit 25 in FIG. 1 according to another embodiment of the presentinvention. Similarly, the input stage 21, the output bias circuit 22,the output stage 23 and the clamping circuit 24 in FIG. 1 arerepresented by an operational amplifier 51. As shown in FIG. 5, thecontrol unit 25 includes a voltage detection circuit 256 and acomparison unit 258. The voltage detection circuit 256 is coupled to thepositive input terminal AVP and the output terminal AVF, for detectingvoltage levels of the positive input terminal AVP and the outputterminal AVF. The comparison unit 258 is coupled to the voltagedetection circuit 256, for determining that the output voltage reachesthe steady state when the voltage difference between the output terminalAVF and the positive input terminal AVP is smaller than a predefinedvalue. Therefore, when the output voltage reaches the steady state, thecontrol unit 25 is able to switch the operating biases VBPOS and VBNOSto the power supply voltage VDDA and the ground voltage GNDA,respectively, so as to deactivate the clamping circuit 24.

Through the above embodiments, the present invention is able to solve aproblem that the clamping circuit cannot be completely closed andtherefore influences the systematic offset voltage of the operationalamplifier. Additionally, circuit characteristics become more stablewithout extra current consumption and area cost for the operationalamplifier.

Please refer to FIG. 6. FIG. 6 is a schematic diagram of a voltageovershoot elimination process 60 according to an embodiment of thepresent invention. The voltage overshoot elimination process 60 is anoperating process of the above output buffer circuit 20, and includesthe following steps:

Step 600: Start.

Step 610: Activate the clamp circuit 24 when the input voltage isreceived.

Step 620: Start to output the output voltage.

Step 630: Deactivate the clamp circuit 24 when the output voltagereaches the steady state.

Step 640: End.

According to the voltage overshoot elimination process 60, the outputbuffer circuit 20 activates the clamp circuit 24 when receiving theinput voltage. Next, the output buffer circuit 20 starts to output theoutput voltage. Not until the output voltage reaches the steady state,does the output buffer circuit 20 deactivates the clamping circuit 24.Operations of the output buffer circuit are detailed in the aboveembodiments, and are not narrated herein.

To sum up, by adding the clamping circuit to the output buffer circuit,the present invention eliminates the voltage overshoot caused by thestrong driving capability of the output stage and avoids the systematicoffset voltage being influenced in the low power application via thetiming control. In addition, the current consumption and area cost ofthe operational amplifier are not increased.

Those skilled in the art will readily observe that numerousmodifications and alterations of the device and method may be made whileretaining the teachings of the invention.

What is claimed is:
 1. An output buffer circuit for avoiding voltageovershoot, the output buffer circuit comprising: an input stage circuitcomprising a positive input terminal, for receiving an input voltage,and a negative input terminal, — the input stage circuit generating acurrent signal according to the input voltage; an output bias circuit,coupled to the input stage circuit, for generating a dynamic biasaccording to the current signal; an output stage circuit, coupled to theinput stage circuit and the output bias circuit, comprising: an outputterminal, reversely coupled to the negative input terminal; and at leastone output transistor, coupled to the output bias circuit and the outputterminal, for providing a driving current to the output terminalaccording to the dynamic bias to generate an output voltage; a clampcircuit, coupled to the input stage circuit, the output bias circuit andthe output stage circuit, for drawing currents from the output terminalto help the current signal to return the dynamic bias to a proper levelwhen the output voltage exceeds a predefined range; and a control unitcontroller, coupled to the clamp circuit, for activating the clampcircuit when the output buffer circuit receives the input voltage andfor deactivating the clamp circuit to prevent a leakage current resultedby flowing through the clamp circuit when the output voltage reaches asteady state.
 2. The output buffer circuit of claim 1, wherein thecontrol unit controller determines the output voltage reaches the steadystate when the output buffer circuit receives the input voltage for apredefined time.
 3. The output buffer circuit of claim 2, wherein thecontrol unit controller comprises: a trigger circuit, for generating atrigger signal when the output buffer circuit receives the inputvoltage; and a timer, coupled to the trigger circuit, for calculatingthe predefined time according to the trigger signal controlling thecontroller to switch a voltage for the clamp circuit to deactivate theclamp circuit after the timer receives the trigger signal and thencounts the predefined time.
 4. The output buffer circuit of claim 1,wherein the control unit controller determines whether the outputvoltage reaches the steady state by detecting voltage difference betweenthe output terminal and the positive input terminal after the outputbuffer circuit receives the input voltage.
 5. The output buffer circuitof claim 4, wherein the control unit controller comprises: a voltagedetection circuit, coupled to the positive input terminal and the outputterminal, for detecting voltage levels of the positive input terminaland the output terminal; and a comparison unit comparator, coupled tothe voltage detection circuit, for determining the output voltagereaches the steady state when the voltage difference between the outputterminal and the positive input terminal is smaller than a predefinedvalue.
 6. The output buffer circuit of claim 1, wherein the clampcircuit comprises: a first metal-oxide-semiconductor field-effecttransistor (MOSFET), comprising a source first terminal coupled to theoutput terminal, a gate second terminal coupled to an operating bias,and a drain third terminal; and a second metal-oxide-semiconductorfield-effect transistor (MOSFET), comprising a source first terminalcoupled to the drain third terminal of the first MOSFET, a gate secondterminal coupled to the output bias circuit and the at least one outputtransistor, and a drain third terminal coupled to the gate secondterminal of the second MOSFET; wherein a level of the operating bias isswitched by the control unit controller.
 7. The output buffer circuit ofclaim 6, wherein the control unit controller switches the operating biasto a first level to activate the clamp circuit when the output buffercircuit receives the input voltage, and switches the operating bias to asecond level to deactivate the clamp circuit when the output voltagereaches the steady state.
 8. The output buffer circuit of claim 7,wherein the first MOSFET and the second MOSFET are both P type MOSFETs,for clamping the output voltage under a predefined high voltage level,and the second level is a power supply voltage.
 9. The output buffercircuit of claim 7, wherein the first MOSFET and the second MOSFET areboth N type MOSFETs, for clamping the output voltage over a predefinedlow voltage level, and the second level is a ground voltage.
 10. Theoutput buffer circuit of claim 1, wherein the input stage circuit is adifferential input stage circuit having a rail-to-rail input range. 11.The output buffer circuit of claim 10, wherein the input stage circuitcomprises an N type metal-oxide-semiconductor (NMOS) differential inputpair and a P type metal-oxide-semiconductor (PMOS) differential inputpair.
 12. The output buffer circuit of claim 1, wherein the output biascircuit comprises a pair of head-to-tail connected complementarymetal-oxide-semiconductor (CMOS) transistors.
 13. The output buffercircuit of claim 1, wherein the at least one output transistor form aclass AB output stage circuit.
 14. A method of avoiding voltageovershoot for an output buffer circuit, the output buffer circuitcomprising an input stage circuit, an output stage circuit and a clampcircuit, the input stage circuit generating a current signal accordingto an input voltage, the output stage circuit generating an outputvoltage according to the current signal, the clamp circuit, coupled tothe input stage circuit and the output stage circuit, for clamping theoutput voltage within a predefined range, the method comprising:activating the clamp circuit when the input voltage is received;starting to output the output voltage; and deactivating the clampcircuit to prevent a leakage current resulted by flowing through theclamp circuit when the output voltage reaches a steady state.
 15. Themethod of claim 14, wherein the step of deactivating the clamp circuitwhen the output voltage reaches the steady state comprises: determiningthe output voltage reaches the steady state when the input voltage isreceived for a predefined time.
 16. The method of claim 14, wherein thestep of deactivating the clamp circuit when the output voltage reachesthe steady state comprises: determining whether the output voltagereaches the steady state by detecting voltage difference between theoutput voltage and the input voltage after the input voltage isreceived.
 17. The method of claim 16, wherein the step of determiningwhether the output voltage reaches the steady state comprises:determining the output voltage reaches the steady state when the voltagedifference between the output voltage and the input voltage is smallerthan a predefined value.
 18. An output buffer circuit for avoidingvoltage overshoot, comprising: an input circuit, configured to generatea current signal according to an input voltage; an output circuit,coupled to the input circuit and configured to generate an outputvoltage according to the current signal; a clamp circuit, coupled to theinput circuit and the output circuit, and configured to clamp the outputvoltage within a predefined range; and a controller, configured toactivate the clamp circuit when the input voltage is received anddeactivate the clamp circuit to prevent a leakage current flowingthrough the clamp circuit when the output voltage reaches a steadystate.
 19. The output buffer circuit of claim 18, wherein the controllerdetermines the output voltage reaches the steady state when the outputbuffer circuit receives the input voltage for a predefined time.
 20. Theoutput buffer circuit of claim 19, wherein the controller comprises: atrigger circuit, for generating a trigger signal when the output buffercircuit receives the input voltage; and a timer, coupled to the triggercircuit, for controlling the controller to switch a voltage for theclamp circuit to deactivate the clamp circuit after the timer receivesthe trigger signal and then counts the predefined time.
 21. The outputbuffer circuit of claim 18, wherein the controller determines whetherthe output voltage reaches the steady state by detecting voltagedifference between the output voltage and the input voltage after theoutput buffer circuit receives the input voltage.
 22. The output buffercircuit of claim 21, wherein the controller comprises: a voltagedetection circuit, coupled to the input circuit and the output circuit,for detecting voltage levels of the input voltage and the outputvoltage; and a comparator, coupled to the voltage detection circuit, fordetermining the output voltage reaches the steady state when the voltagedifference between the output voltage and the input voltage is smallerthan a predefined value.
 23. The output buffer circuit of claim 18,wherein the input circuit is a differential input circuit having arail-to-rail input range.
 24. The output buffer circuit of claim 18,further comprises an output bias circuit coupled to the input circuitand the output circuit, for generating a dynamic bias according to thecurrent signal.